1. Field
Various embodiments of the present invention relate to a complementary metal oxide semiconductor (CMOS) image sensor, more particularly, to an analog-to-digital converter and a CMOS image sensor including the same.
2. Description of the Related Art
FIG. 1 is a block diagram illustrating a conventional CMOS image sensor including an analog-to-digital converter of a column parallel scheme.
Referring to FIG. 1, the conventional CMOS image sensor includes a row driver 110, an active pixel array 120, an optical black (OB) pixel array 122, that is, a dummy pixel array, an analog-to-digital converter 145 including a reference voltage generator 130, a correlated double sampling (CDS) array 140 and a ramp signal generator 160, and a digital code output unit 150.
The row driver 110 generates various control signals RX, TX and SEL for controlling pixels of the active pixel array 120 and the OB pixel array 122. The active pixel array 120 outputs an active pixel signal APS_O corresponding to each column, and the OB pixel array 122 outputs an OB pixel signal OB_O as a column signal.
Since a power voltage which is the same as a power supply voltage provided to the active pixel array, is provided to the OB pixel array 122, it may be possible to transfer a noise which is the same as a power supply voltage noise, hereinafter, referred to as “a power noise”, generated in the active pixel array 120 through the OB pixel signal OB_O. An upper portion of the OB pixel array 122 is doped with a material, which blocks a light from passing through the OB pixel array 122, and the OB pixel array 122 may efficiently transfer the power noise using a block level signal.
The analog-to-digital converter 145 includes the reference voltage generator 130, the CDS array 140 and the ramp signal generator 160. The reference voltage generator 130 generates a correlated double sampled OB sampling signal from the OB pixel signal OB_O based on the OB pixel signal OB_O and a first ramp signal RAMP_R, and generates a second reference voltage REF_C based on a first reference voltage REF_OB and the generated OB sampling signal.
The CDS array 140 receives an active pixel signal APS_O, a second ramp signal RAMP_C and the second reference voltage REF_C, and generates an active sampling signal of correlated double sampling from the active pixel signal APS_O based on the active pixel signal APS_O and the second ramp signal RAMP_C. The CDS array 140 compares the generated active sampling signal with the second reference voltage REF_C to generate a comparison result signal CDS_O for generating a digital code.
The first ramp signal RAMP_R and the second ramp signal RAMP_C may be generated from the ramp signal generator 160. Since a noise element may occur in the ramp signal generator 160, the first ramp signal RAMP_R and the second ramp signal RAMP_C may be generated by a single ramp signal generator. The first ramp signal RAMP_R for generating a reference voltage which is different from the second ramp signal RAMP_C, and maintains a uniform voltage level without changing the voltage level before or after, a ramp operation is performed.
The digital code output unit 150 receives the comparison result signal CDS_O from the CDS array 140, and generates the digital code value for a digital signal processing of an image signal processor (ISP) based on the comparison result signal CDS_O.
FIG. 2 is a detailed diagram of the reference voltage generator 130 and the CDS array 140 shown in FIG. 1.
Referring to FIG. 2, the reference voltage generator 130 may include an OB CDS circuit 132 for generating the OB sampling signal on an input node IN_OB of a differential comparator A1 and an output amplifier A3 for buffering the OB sampling signal to generate a second reference voltage REF_C.
The OB CDS circuit 132 may include a comparison unit 133, a signal transmission capacitor C3 coupled to the comparison unit 133, a fourth switch S4 coupled to the signal transmission capacitor C3 in parallel and an amplifier A2.
The comparison unit 133 may include a first switch S1 for controlling a transmission of an OB pixel signal OB_O, a second switch S2 for controlling a transmission of a first ramp signal RAMP_R, a blocking capacitor coupled between the first switch S1 and the second switch S2, a storage capacitor C2 coupled to the first switch S1 for providing an OB sampling signal, a third switch S3 coupled to the differential comparator A1, and the differential comparator A1. The comparison unit 133 receives the OB sampling signal and compares the OB sampling signal with a first reference voltage REF_OB.
The blocking capacitor C1 transfers a voltage variation amount irrespective of a voltage level of the ramp signal.
The CDS array 140 includes a first active CDS circuit 142, a second active CDS circuit 144, and an Nth active CDS circuit 146 at each column, which are operated based on a first active pixel signal APS_O_1, a second active pixel signal APS_O_2, an Nth active pixel signal APS_O_n. Each of the active CDS circuits 142, 144 and 146 has a same structure as the OBCDS circuit 132 of the reference voltage generator 130.
A power supply voltage provided to the active pixel array 120 is provided to the OB pixel array 122 and the reference voltage generator 130. A noise element of an active sampling operation may be removed through a reference voltage, which is generated using the OB CDS circuit 152 having a same structure as the active CDS circuits 142, 144 and 146.
However, since a conventional noise reduction scheme as described above reduces a power noise of a pixel by generating a reference voltage using the OB pixel signal OB_O outputted from the OB pixels, that is, dummy pixels, which are arrayed in a column direction, and using the generated reference voltage as a reference voltage of all active pixel columns, the conventional noise reduction scheme has demerits since a separate reference voltage generator and many OB pixels for obtaining a representative value are needed.
Moreover, since the conventional noise reduction scheme obtains the representative value, the accuracy is lowered, and the power noise of the pixel is not perfectly removed.
In the conventional noise reduction scheme, when the reference voltage generator performs a process of the OB pixel signal OB_O, the first reference voltage REF_OB and an additional circuit, for example, an output amplifier A3, may be a different noise source.